Simple and gate program in verilog

Here is the truth table:. Now let us try to understand the code. In verilog, one circuit is represented by set of "modules". We can consider a module as a black box. With this assumption, if you draw a block diagram of the circuit with a set of signals connection each other, that is called top level design. Then go on writing modules for each black box, then design that black box with in the same way.

This is how we are designing a circuit. You will understand this concept after studying some examples. Go back to the example. Here, module is keyword, andgate is the name given to the module in this examples and a, b and y are the ports or connections to the module. Every modules and with the keyword endmodule. In the beginning of a module, we have to declare all ports as input output or inout. By default, ports will have one pin or one bit. Using 'assign' statement, we connected inputs and outputs via AND gate.

Here, we are not going to store the values, and hence we did not declare any registers. Then endmodule is used to terminate the module. Behavioral modeling is the highest level of abstraction in the Verilog HDL. All that a designer need is the algorithm of the design, which is the basic information for any design. This level simulates the behavior of the circuits; the details are not specified. Just a simple truth table would suffice. In this case, the port list includes the output and input ports.

When our level of abstraction is behavioral level, then we use reg datatype in the output ports. The reg data object holds its value from one procedural assignment statement to the next and means it holds its value over simulation data cycles. Using the always statement, a procedural statement in Verilog , we run the program sequentially.

A, B is known as the sensitivity list or the trigger list. The sensitivity list includes all input signals used by the always block. It controls when the statements in the always block are to be evaluated. In Verilog, begin embarks and end concludes any block which contains more than one statement in it. Now, we have,. The condition for AND gate is that if both the inputs are high, then the output is also high, else in every other condition that has to be low. The file to be included and the name of the module changes, but the basic structure of the testbench remains the same in all the three modeling styles.

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